IIT School Lecturers

Dr. Michael Current has been active in the use of ion beams for doping, lamination and analysis of electronic materials and metals for 5 decades and has been an instructor at the IIT school since 1982. He has worked as a process engineer, researcher and teacher for such companies as Signetics/Philips, Xerox/PARC, Applied Materials, Frontier Semiconductor and numerous start-up operations. Dr. Current was the founding president of the Silicon Valley Ion Implant Users Group in 1983 and has taught implant and metrology courses at Kyoto U., Stanford, UC Berkeley, Santa Clara U. and Nat. Cheng Kung U.(Taiwan). He has published over 260 papers and book chapters and is currently CTO of Silicon Genesis, engaged in using high-dose proton implants for transfer of CMOS device layers for 3DIC stacking.

Ion implantation was the critical innovation the catalyzed the integrated circuit industry in 1975-77 into an exponential growth in the following decades. This history reviews the landmarks of solid-state electronics, showing its early slow growth of about 10% per year for its first 70 years. Suddenly 3 innovations associated with ion implantation in the early 1970's cut the cost of integrated circuit manufacturing by 70%. This enabled the exponential growth of microelectronics and extended uses for ion implanters.

Dr. Thomas N. Horsky is a consultant to the semiconductor equipment industry. He is credited with the development of the indirectly-heated cathode source, the leading implanter source in use today. Tom has authored more than fifty U.S. patents, and has published over seventy-five articles. He is also a founder of SemEquip, Inc., a company focused on developing commercial ion sources and related technologies. SemEquip was eventually merged with Nissin to form the Nissin Ion Equipment USA R&D center (Billerica, MA), which he managed until 2017.

This talk will be a detailed discussion of ion source technology as it relates to commercial ion implantation. The goal of the presentation is to provide a concrete aid to students and professionals working in, or seeking to work in, the ion implantation industry. Practical guidance will be given regarding operation and troubleshooting, as well as the conceptual underpinnings of ion sources in use today.

Dr. Bo Vanderberg is Senior Director of Technology and a Fellow at Axcelis Technologies, with thirty years of experience in ion implantation system development. His work spans ion source engineering, beamline architecture, and advanced control systems, and he played a lead role in the creation of the Purion high current platform. Before joining Axcelis, he conducted postdoctoral research at Uppsala University in Sweden and served as a Visiting Scientist at MIT and Northeastern University. He is the author of several book chapters on ion implantation systems.

Modern ion implanters rely on tight control of charged particle beams to achieve energy and mass purity, angle stability, uniform dose delivery, and safe wafer charging across logic, memory, power and image sensor applications. In this talk, we cover the basic theories and concepts for beam transport, from source extraction and emittance control, through mass and energy selection and scanning, to end-station interactions at the wafer, together with closed-loop controls (dosimetry, angle, charge) and equipment/fab integration needed to maintain process windows. We illustrate different beamlines and process requirements with applications and briefly discuss implanter reliability.

Dr. Michael Current has been active in the use of ion beams for doping, lamination and analysis of electronic materials and metals for 5 decades and has been an instructor at the IIT school since 1982. He has worked as a process engineer, researcher and teacher for such companies as Signetics/Philips, Xerox/PARC, Applied Materials, Frontier Semiconductor and number of start-up operations. Dr. Current was the founding president of the Silicon Valley Ion Implant Users Group in 1983 and has taught implant and metrology courses at Kyoto U., Stanford, UC Berkeley, Santa Clara U. and Cheng Kung U.(Taiwan). He has published over 260 papers and book chapters and is currently CTO of a Silicon Valley startup using high-dose proton implants for transfer of CMOS device layers for 3DIC stacking.

Ion implantation processing of electronic materials and devices use a wide variety of acceleration components and target chambers (end stations) as well as many special technologies. Each of the components are designed and combined to operate in a diverse array of operating conditions for ion energy, beam current and dose. After an outline of the form and function of typical implanter components, examples of commercial ion implantation systems will be reviewed for medium and high currents, high energy, plasma immersion as well as specialized tools for doping of large-area flat-panels of Si-on-glass and photo-voltaic cells.

Dr. Wilfried Lerch earned his PhD in Physics from the Westfälische Wilhelms-University in Münster, Germany. He began his career at AST elektronik GmbH, which later became Mattson Thermal Products GmbH, where he worked as Director Technology. In 2008, he joined centrotherm international AG, leading R&D and technology development for front-end and back-end semiconductor products. His responsibilities included tools for annealing electronic materials, horizontal and vertical furnaces, RTP systems, low-temperature plasma oxidation, high-temperature tools for SiC and GaN, as well as soldering tools. In 2018, Dr. Lerch founded Skylark.Solutions, a pure semiconductor technology consulting company. In 2020, he joined the Fraunhofer Institute for Electronic Microsystems and Solid-State Technologies (EMFT) as Head of the Silicon and Device (SiD) department, since early 2025 focusing especially on enabling, new technologies and devices. Dr. Lerch serves as co-chair of the German RTP User Group and is an active member of the Semiconductor Technology Committee at SEMI Europe. He has authored over 100 publications on annealing technologies and is the author of a book on RTP technology.

Thermal processes are essential in semiconductor manufacturing, particularly for creating highly conductive, ultra-shallow junctions in CMOS transistors as dimensions shrink. Over the past decades thermal budget reduction was continuously combined with thermal process development. Temperature-time cycles have evolved from furnace-based minutes through halogen lamp-based annealing lasting seconds to spike anneals, flash-lamp annealing, and laser annealing, offering millisecond temperature peaks ideal for activation. Other processes that have historically been thermally driven such as oxidation of silicon have also migrated to process solutions using other drivers such as plasma activation. This contribution reviews various annealing equipment types and their annealing schemes (temperature-time cycles, gaseous ambient etc.) and investigates the formation of ultra-shallow, highly-electrically-activated and custom-shaped junctions combined to defect annealing. Furthermore, deactivation by sequential processes will be reviewed. Finally in this compilation the activation techniques in diamond-like semiconductor Germanium and in wide-band-gap semiconductors SiC and GaN are described in detail.

Mathias Rommel received his PhD in Electrical Engineering on carrier lifetime spectroscopy and oxide characterization in 2007 from the University of Erlangen. From 1995 to 2001 he was teaching and research assistant at the Chair of Electron Devices at the University of Erlangen focusing on contamination control and electrical device characterization. In 2002 he joined the Fraunhofer Institute for Integrated Systems and Device Technology (IISB) in Erlangen being responsible for the nanotechniques group since 2006 with additional research focus on nanopatterning by focused ion beam (FIB), nanoimprint lithography (UV-NIL and UV-SCIL) as well as electrical scanning probe microscopy (SPM) techniques for the characterization of high-k layers and semiconductor materials. Since several years, he also focused on the in-depth characterization of defects in 4H-SiC by means of carrier lifetime measurements and deep level transient spectroscopy (DLTS). Starting in 2021, IISB’s 4H-SiC CMOS circuits activities for high temperature applications complement his responsibilities. He authored or co-authored more than 170 Scopus listed publications.

Ion implantation requires comprehensive metrology to control doping profiles, verify dopant activation, and detect process-induced defects. This talk reviews essential characterization techniques organized into three complementary categories: microanalytical methods (SIMS, TEM, APT) for compositional and structural analysis, optical methods (photoluminescence, photomodulated reflectance) for rapid non-destructive assessment of as-implanted damage and post-anneal activation, and electrical techniques (four-point probe, spreading resistance profiling, C-V) for direct measurement of device-relevant parameters. Emphasis is placed on the complementary nature of these approaches and the need for appropriate technique selection. Beyond these established methods, the talk will also exemplarily discuss emerging and laboratory-level characterization techniques that promise enhanced sensitivity or resolution for next-generation device structures and wide bandgap semiconductors.

Dr. David Kirkwood received a BSc in Chemistry from the University of Edinburgh in 1993 and a doctorate in Chemical Physics from the University of Sussex in 1996. After several years conducting research in spectroscopy in both Switzerland and the UK, he joined Applied Materials in early 2001 and has since spent over 22 years working closely with customers on process cleanliness improvement in ion implantation at both Applied Materials and Axcelis Technologies, where he is currently the Director of Innovation in the Technology Development group. Dr. Kirkwood is an Axcelis Distinguished Technologist and is also a registered patent agent with the USPTO.

Many factors in the design, construction materials and operation of ion implanters can compromise the expected precision and cleanliness of ion implantation processes. Issues to be discussed are: (1) “mass overlaps” resulting from molecular ion breakups and charge exchanges, (2) transport of energetic and vapor phase metals and dopants, (3) wetting of device structures by contaminant-laden water vapor during load-lock pump down and following cryo-implants, (4) organic contamination from vacuum pump oils (5) particle transport, adhesion, ion blocking and out-diffusion effects.

With a career spanning over 35 years, Ewald Wiltsche is a renowned expert in ion implantation equipment and technology. His journey began as a maintenance technician at Siemens in 1987, followed by a long-standing tenure at Infineon since 1999, where he is now responsible for ensuring radiation safety and driving equipment engineering innovations for ion implantation and laser annealing. Among his notable contributions are the development of groundbreaking innovation for new technologies, including single wafer handling solution for thinned 300 mm wafer substrates and high-efficiency ion sources with sputtered ions for leading edge technologies.

This lecture provides an overview of key safety considerations for two critical semiconductor manufacturing technologies: ion implantation and thermal annealing. Ion implanters are among the most complex tools in semiconductor fabs and involve several inherent hazard categories, including high voltage, hazardous materials, radiation, mechanical risks, and ergonomic challenges. Although extensive safety features are integrated into the design of ion implantation equipment, the potential for serious injury remains—especially when safety interlocks or checks are overridden or when recommended procedures are not followed. Safety incidents occur most frequently during maintenance operations, where personnel interact directly with hazardous components. We summarize the major hazard classes, discuss their interactions, highlight differences between operational, maintenance, and service conditions, and outline recommended practices for safe tool operation and servicing.

The second part of the lecture reviews safety aspects of annealing systems, which operate at elevated temperatures and may use or generate hazardous gases, reactive species, or volatile compounds released from various wafer materials. Systems such as rapid thermal processing (RTP) and flash lamp annealing incorporate high temperatures, intense radiation, and significant electrical power, all of which can pose risks despite comprehensive CE and SEMI S2/S8 safety measures. Residual risks nevertheless remain and understanding them is essential. We describe the main hazard categories associated with annealing tools and propose procedures to ensure safe operation, effective maintenance, and ergonomically sound handling.

Silke Hamm began her career as an Equipment Engineer at the Fraunhofer Institute for Integrated Systems and Device Technology (IISB) in Erlangen, focusing on oxidation and LPCVD furnace systems. In 1998, she joined Mattson Thermal Products GmbH, where she initially worked as an Equipment Engineer specializing in temperature measurement and control. She later transitioned into the role of Process Engineer with a strong emphasis on implant annealing, particularly spike annealing, and has authored numerous publications in the field of rapid thermal processing (RTP). Today, she serves as the Manager of the Application Laboratory, where she is responsible for ensuring the smooth operation of all laboratory equipment and systems, as well as overseeing laboratory and gas safety.

This lecture provides an overview of key safety considerations for two critical semiconductor manufacturing technologies: ion implantation and thermal annealing. Ion implanters are among the most complex tools in semiconductor fabs and involve several inherent hazard categories, including high voltage, hazardous materials, radiation, mechanical risks, and ergonomic challenges. Although extensive safety features are integrated into the design of ion implantation equipment, the potential for serious injury remains—especially when safety interlocks or checks are overridden or when recommended procedures are not followed. Safety incidents occur most frequently during maintenance operations, where personnel interact directly with hazardous components. We summarize the major hazard classes, discuss their interactions, highlight differences between operational, maintenance, and service conditions, and outline recommended practices for safe tool operation and servicing.

The second part of the lecture reviews safety aspects of annealing systems, which operate at elevated temperatures and may use or generate hazardous gases, reactive species, or volatile compounds released from various wafer materials. Systems such as rapid thermal processing (RTP) and flash lamp annealing incorporate high temperatures, intense radiation, and significant electrical power, all of which can pose risks despite comprehensive CE and SEMI S2/S8 safety measures. Residual risks nevertheless remain and understanding them is essential. We describe the main hazard categories associated with annealing tools and propose procedures to ensure safe operation, effective maintenance, and ergonomically sound handling.

Kevin S. Jones is a professor and former chairman of the department of Materials Science and Engineering at the University of Florida (Gainesville). He is co-director off the Software & Analysis of Advanced Materials Processing Center (SWAMP). He has spent the past 30 years as a professor studying processing-induced defects in semiconductors, focusing mainly on transmission elector microscopy (TEM) characterization of defects after ion implantation of various materials and developing an understanding of how defect evolution influences dopant diffusion in electronic materials. He has published over 300 papers in the field of ion implantation and is Chairman of the International Committee on Ion Implantation Technology.

This talk will explore the origin of radiation damage that occurs during ion implantation of Silicon. This includes the formation of point defects, vacancies and interstitials, damage accumulation and amorphization of Si by both dopant and non-dopant ions.

Dr. Wilfried Lerch earned his PhD in Physics from the Westfälische Wilhelms-University in Münster, Germany. He began his career at AST elektronik GmbH, which later became Mattson Thermal Products GmbH, where he worked as Director Technology. In 2008, he joined centrotherm international AG, leading R&D and technology development for front-end and back-end semiconductor products. His responsibilities included tools for annealing electronic materials, horizontal and vertical furnaces, RTP systems, low-temperature plasma oxidation, high-temperature tools for SiC and GaN, as well as soldering tools. In 2018, Dr. Lerch founded Skylark.Solutions, a pure semiconductor technology consulting company. In 2020, he joined the Fraunhofer Institute for Electronic Microsystems and Solid-State Technologies (EMFT) as Head of the Silicon and Device (SiD) department, since early 2025 focusing especially on enabling, new technologies and devices. Dr. Lerch serves as co-chair of the German RTP User Group and is an active member of the Semiconductor Technology Committee at SEMI Europe. He has authored over 100 publications on annealing technologies and is the author of a book on RTP technology.

Diffusion phenomena play a critical role in semiconductor processing, particularly in the behavior of dopants and point defects. The distribution of point defects, influenced by annealing and preceding steps such as ion implantation or thermal oxidation, directly impacts dopant diffusion and electrical activation. Elevated temperatures during processing can cause dopant atoms and impurities to diffuse, broaden their distribution, and undergo quasi-chemical reactions with other atoms or intrinsic defects. These interactions often result in reduced electrical activation compared to the total dopant concentration. Annealing processes are intentionally employed to drive dopants deeper into semiconductors, activate implanted dopants, and repair implantation-induced damage. However, diffusion and reduced activation can occur during any high-temperature process, whether in front-end or back-end processing. This chapter outlines the key concepts of diffusion in semiconductors, with a focus on silicon.

Sean Jones received his Bachelors in Physics from the University of Florida and his PhD in Materials Science from Colorado School of Mines. With 6 years of semiconductor experience between Intel and Axcelis, he is currently a Senior Scientist at Axcelis Technologies. Sean’s research interests focus on wafer handling and characterization, especially for power applications.

Any process involving the ion implantation into a crystalline substrate should take ion channeling into account. Whether it is a process condition to be targeted or avoided, channeling is the alignment of ion trajectories with crystal planes in the target. This alignment reduces stopping power, changing the implant depth profile and increasing the average implant depth by as much as three times. This class links crystallographic fundamentals to real-world results while covering decades of research into silicon and silicon carbide.

Dr. Leonard Rubin received an B.S. degree in Materials Science and Engineering and M.S and PhD. degrees in electronic materials from Massachusetts Institute of Technology. He worked at Zilog Inc. in Nampa, ID in ion implantation, diffusion and rapid thermal processing. He has been at Axcelis since 1995, where he is Chief Device Scientist and an Axcelis Fellow. Throughout this time, he has been engaged in the research and development of ion implantation, rapid thermal processing on advanced CMOS devices, with particular emphasis on the effects of implant temperature and implant beam incidence angle. More recently he has focused on ion implantation applications in CMOS image sensors.

Ion implantation is essential for fabrication of advanced CMOS devices. The flexibility and precision of ion implantation in the selection of dopant species, spatial location with the device, and subtle control of concentration profiles enables rapid introduction of new process technologies with optimization or even elimination of performance tradeoffs. This presentation will review the history, present functions and future trends of ion implantation for doping and non-doping (material modification) application for planar and three-dimensional (FinFET) CMOS transistors, including memory and image sensors.

Dr. Werner Schustereder received his PhD degree in Ion Physics at the University of Innsbruck, Austria. After working at the Max Planck Institute for Plasma Physics in Munich on material science for nuclear fusion power plants, he joined Infineon Technologies Austria AG in 2008. Werner is a Senior Principal Engineer for Process Development in Ion Implantation and Laser Thermal Annealing, he teaches courses at various levels, supervises diploma and PhD students and presents at international conferences. Werner is co-author of 70+ peer-reviewed publications and 50+ active patents on methods for fabricating power devices. Werner is a member of the IIT International Committee and co-chair of the German Ion Implantation Users Group, organizing the periodic knowledge exchange forum of the German-speaking Ion Implantation community.

Semiconductor power devices are a foundational pillar of the global, electrified economy, enabling decarbonization and digitalization from consumer to industrial, automotive, and data center applications. Meeting relentless demands for higher efficiency, switching performance, and reliability increasingly depends on ion implantation. Beyond typical wafer frontside processes known from CMOS, power devices might also require precise wafer backside implantation processes and bulk engineering to form junctions, edge terminations, compensation and isolation structures. Thereby tight control of energy, dose, angle, and wafer temperature are essential. As product platforms expand with wide bandgap materials, ion implantation becomes even more important. In SiC, negligible dopant diffusion necessitates chained implant sequences with multiple energies to create extended dopant profiles, precise angle control for channeling and careful crystal damage management for region of high dopant concentration. In GaN, implantation is pivotal for isolation in HEMT devices.

This chapter reviews the economic importance of power devices, their technological trends, why and how WBG complements silicon, and the crucial impact of ion implantation processes for various power technologies.

Santosh K. Kurinec is a Professor of Electrical and Microelectronic Engineering at Rochester Institute of Technology (RIT). She is a Fellow of IEEE and a Member of the New York Academy of Sciences. She is a Guest Professor at Technical University of Applied Sciences Würzburg-Schweinfurt, Germany. She worked at IBM Watson Research Center as a visiting scholar. Her research activities include advanced integrated circuit materials & devices and photovoltaics. She is currently working on addressing energy consumption in semiconductor manufacturing and offsetting using renewables. She received the 2012 IEEE Technical Field Award for integrating research into teaching to prepare microelectronic engineers for future challenges. She was inducted in the Women in Technology International Hall of Fame in 2018. She received IEEE Region 1 William Terry Distinguished Service Award, 2022, for IEEE service, research and teaching. In 2024, she is appointed as Vice Chair of IEEE SRC Region 1-3, 7 and she is an IEEE EDS Distinguished Lecturer. She has over 140 publications in research journals and conference proceedings. She edited books on Energy Efficient Computing & Electronics: Devices to Systems, and Nanoscale Semiconductor Memories: Technology and Applications, and Emerging Photovoltaic Materials: Silicon & Beyond.

The scaling of complementary metal oxide semiconductor (CMOS) is evolving towards stacked nanosheets complementary field effect transistors (CFETs). In a CFET configuration, NMOS and PMOS devices are vertically stacked, which are realized using multilayer epitaxial depositions and selective etchings. These advancements require innovations in lithography, device architecture, material & process engineering and design technology co-optimization (DTCO) when combined at standard cell level. These include, among others, advanced interconnect and middle-of-line schemes and the introduction of backside power delivery. This chapter will provide a comprehensive overview of the technological advances enabling CFETs towards sub nm scaling.